Available Datasheets
List of IP blocks:

# IP Name
(Click for Datasheet)		 IP Description Test Chip Packaged Parts Testing
Status		 Process Application Differentiation
1 PMCC_DIV60G IP block includes a high speed (up to 60GHz) fully differential static frequency divider by 2. IC features input active balun and I/Q outputs. PMCC810 QFN 20pin Functionality test is done on bare die to measure the maximum dividing frequency. Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Ultra high frequency prescaler on 0.18um SiGe. DC to 60GHz, SE or DIFF inputs, I/Q DIFF outputs.
2 PMCC_DIV50G1_16 50GHz Programmable Prescaler -Divider by 1/2/4/8/16 PMCC800  QFN 20pin No testing is done Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment DC to 50GHz, programmable divide coefficients SE or DIFF inputs, DIFF outputs.
3 PMCC_VCO25G5CR 25.5GHz Colpitts VCO PMCC900 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe. 
5 PMCC_VCO26GC 26GHz Colpitts VCO PMCC902 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
6 PMCC_VCO25GC 25GHz Colpitts VCO PMCC903 QFN 20pin No testing is done Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
7 PMCC_VCO24G5C 24GHz Colpitts VCO PMCC904  None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
8 PMCC_VCO27GCR 27GHz Colpitts VCO with reversed varactor polarity PMCC905 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
9 PMCC_VCO25G5CR 25GHz Colpitts VCO with reversed varactor polarity PMCC907 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
10 PMCC_VCO27GCM 25GHz Colpitts VCO with MOS varactor PMCC908 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Low noise differential architecture. Low cost process 0.18um SiGe.
11 PMCC_VCO10GC 10GHz Colpitts VCO PMCC909 None   Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
12 PMCC_VCO11GC 11GHz Colpitts VCO
13 PMCC_VCO12GC 12GHz Colpitts VCO
14 PMCC_VCO16GC 16GHz Colpitts VCO PMCC910  None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
15 PMCC_VCO18GC 18GHz Colpitts VCO
16 PMCC_VCO20GC 20GHz Colpitts VCO
17 PMCC_VCO8GN 8GHz Negative Impedance VCO PMCC911 None - Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
18 PMCC_VCO14GN 14GHz Neg Impedance VCO
19 PMCC_VCO14GC 14GHz Colpitts VCO
20 PMCC_VCO10GN 10GHz Neg Impedance  VCO PMCC912 QFN 20pin No testing is done Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
21 PMCC_VCO11GN 11GHz Neg Impedance VCO
22 PMCC_VCO12GN 12GHz Neg Impedance VCO
23 PMCC_VCO16GN 16GHz Neg Impedance  VCO PMCC913 None   Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
24 PMCC_VCO18GN 18GHz Neg Impedance VCO
25 PMCC_VCO20GN 20GHz Neg Impedance VCO
26 PMCC_VCO24GN 24GHz Neg Impedance  VCO PMCC914 QFN 20pin No testing is done Jazz 0.18um SiGe SBC18HX PLLs, Broadband test and measurement equipment Triple VCO on a single chip. 
27 PMCC_VCO25GN 25GHz Neg Impedance VCO
28 PMCC_VCO26GN 26GHz Neg Impedance VCO
29 PMCC_IRM30G Up to 30GHz) fully differential double balanced mixer IP block. PMCC820 None - Jazz 0.18um SiGe SBC18HX 30GHz wireless transmitters. Low cost SiGe implementation.
30 PMCC_EAMD12G EA/MZ Modulator Driver. Designed for direct driving of the EA or MZ Modulators or EML devices at data-rates up-to 11.3Gbps. Programmable output voltage swing as well as monitoring, crossing point control, and programmable output DC offset (bias). Fully differential architecture.  - - - Jazz 0.18um SiGe SBC18HX Electro Absorption and MZ modulators and DFB lasers in fiber optic communications;
broadband high output swing Limiting Amplifiers from DC to 12Gb/s.		 3V adjustable swing and DC offset. Cross point monitoring and ajusting. Low cost SiGe implementation.
31 PMCC_DSER12G The macro-block is designed for robust 8.5- 11.3Gb/s data/clock recovery and independent on data coding and demultiplexing 1:32.  Will be tested by a customer on an ASIC - - IBM 65nm 10LPe SONET/SDH OC-192 receiver/CDR PHY 10Ge receiver with deserializer.
10G back planes. XFI receiver with deserialization (both line and host side)		 Implemented
based on differential CML logic. Extra low power, 15mV input sensitivity. IBM 65nm CMOS technology. Includes CDR, Equalizer, LOS, LOL, frac N divider.
32 PMCC_SER12G The IP block is designed for robust  32:1 serialization of 8.5-11.3Gb/s data independent on data coding.  Will be tested by a customer on an ASIC - - IBM 65nm 10LPe SONET/SDH OC-192 transmitter with CMU. PHY 10GbE transmitter.
10G back planes. XFI transmitter with serialization (both line and host side)		 Implemented
based on differential CML logic. Line rate output data retiming. Extra low power, 500mV SE output swing. IBM 65nm CMOS technology. Includes CMU, with frac N PLL.
33 PMCC_SERDES12G The IP block is a serializer/deserializer designed for robust  32:1 /1:32 serialization of 8.5-11.3Gb/s data independent on data coding.  Will be tested by a customer on an ASIC - - IBM 65nm 10LPe SONET/SDH OC-192 transmitterand receiver with CDR/CMU. PHY 10GbE transceiver.
10G back planes. XFI transmitter and receiver with serialization and deserialization (both line and host side)		 Extra low power. Implemented
based on differential CML logic - high noise immunity. Line rate output data retiming. 500mV SE output swing. IBM 65nm CMOS technology. Includes CMU, with frac N PLL.
34 PMCC_PLL12G The IP block is designed as a complete CMU X32 producing 8.5-11.3GHz output clock. Fully differential architecture Will be tested by a customer on an ASIC - - IBM 65nm 10LPe SONET/SDH OC-192 compliant transceivers supporting multiple clocking mode Extra low power. Implemented CMU supports different clocking modes: FEC+G.709, FEC only,  G.709, FEC to G709 frame.
35 PMCC_SER32G The IP block is designed for robust  32:1 serialization of 32Gb/s data independent on data coding. CMU X16 is provided. - - - 45nm IBM SOI CMOS technology. 100GbE fiber optic communications. Instrumentation. Extra low power (10mW MUX core). Implemented
based on differential CML logic - high noise immunity. 400mV SE output swing. 45nm IBM SOI CMOS technology. Includes CMU, with frac N PLL.
36 PMCC_VCOMB12G The IP block is a low noise multi-band differential LC voltage controlled oscillator (VCO). Will be tested by a customer on an ASIC - - IBM 65nm 10LPe

Phase-locked loops.
CMU for fiber optic applications.
Reference clock generators.		 Extra low power. Wide frequency range. When used in CMU supports different clocking modes: FEC+G.709, FEC only,  G.709, FEC to G709 frame.

Note: all IP blocks are designed for +/-3s process variation and temperature range -25+125C.